Process Hierarchy

If you are interested in this process, either by itself or as part of a longer processing sequence, please send us email at engineering@mems-exchange.org or call us at (703) 262-5368
  Silicon Cap wafer preparation
Process characteristics:
Cavity etch
Mark yes, if you wish to have a partial etch in the substrate to create cavities.
Cavity etch*
yes no
Mark yes, if you wish to have a partial etch in the substrate to create cavities.
Depth
Depth of cavity. Depth < thickness of wafer for partial etch.
Depth*
Depth of cavity. Depth < thickness of wafer for partial etch., must be 50 .. 350 µm
50 .. 350 µm
Through wafer etch
Mark yes, if you wish to create holes that go completely through the substrate.
Through wafer etch*
yes no
Mark yes, if you wish to create holes that go completely through the substrate.
Etch type dry anisotropic
Material silicon
Comments:
  • This module allow preparation of silicon cap wafer for packaging applications.
  • This modules requires a mask.